Blog
Deep-dives on PCB design, signal integrity, and semiconductor test from 25+ years in the field.
Technical Guide · High-Speed Memory
Most DDR failures start before routing. The placement, stackup, routing, impedance, and timing rules every PCB designer should know for DDR4 and DDR5 memory interfaces.
September 26, 2026 · Read article →
Technical Guide · ATE Platforms
Two dominant ATE platforms, two very different sets of constraints. What actually changes in the PCB when you move a program from Advantest V93000 (93K) to Teradyne UltraFLEX.
July 26, 2026 · Read article →
Technical Guide · Wafer-Level Test
A practical engineering reference for designing probe cards that survive wafer-level testing at modern data rates — covering electrical design, MEMS vs. cantilever trade-offs, and notes on Advantest 93K and Teradyne J750.
June 21, 2026 · Read article →
