DDR4 & DDR5 Routing and Placement Guidelines

1. Placement strategy

• Place memory devices or DIMM connectors as close to the memory controller as practical to reduce routing length and simplify timing closure.
• Plan placement together with the pin escape strategy. Byte lane organization, DQ and DQS access, power delivery, and via locations should be considered before final placement.
• Keep decoupling and bypass capacitors close to the relevant devices.
• For complex multi-device layouts, use a proven topology and consider signal flow before rotating or moving memory devices.

2. Stackup strategy

• Freeze the PCB stackup at the beginning of the design, because dielectric thickness, dielectric constant, copper thickness, and layer arrangement directly affect impedance and propagation delay.
• A strong starting concept is Ground | Signal | Ground, keeping critical memory routing close to a solid reference plane.
• Use upper inner signal layers close to the controller and memory devices for DQ and DQS.
• Avoid adjacent routing layers where possible to reduce inductive crosstalk.
• Select trace width, spacing, dielectric material, and layer height together so impedance and timing targets can be achieved.

3. Routing strategy

• Keep DQ and DQS signals of the same byte group on the same routing layer.
• Give data and strobe signals priority during layer assignment.
• Minimize vias: limit DDR4 and DDR5 data and strobe signals to two vias per signal.
• Keep each data byte on a single internal routing layer whenever practical.
• Avoid unnecessary layer changes in command, address, and control routing.
• Avoid changing layers between DIMMs in multi-slot topologies.
• Use blind or back-drilled vias where appropriate to reduce via stub effects.
• Place a nearby ground stitching via when a signal changes layers, within a 50 mil radius for a common reference plane transition.
• Use chevron-style routing where possible to create space for ground stitching vias.
• Add ground vias around the controller and memory devices to improve the signal return path.
• Maintain controlled spacing between signal groups based on the reference plane distance.
• For fly-by topologies, maintain a consistent routing structure and place required terminations at the end of the topology.

4. Impedance and timing

• AMD Versal reference designs specify 50 Ω single-ended and 90 Ω differential impedance for DDR4.
• DDR5 reference values are 40 Ω single-ended and 75 Ω differential. Always confirm the exact values for the selected controller and memory device.
• Match propagation delay and skew relationships rather than blindly making every trace the same length.
• For the DDR4 example, DQ-to-DQS skew is constrained to ±100 ps.

5. Final verification

• Perform pre-layout and post-layout timing analysis.
• Verify impedance, eye quality, jitter, noise margin, DQ-to-DQS skew, and power-aware signal integrity.
• For DDR5, consider channel loss and equalization during SI analysis. IBIS-AMI based analysis can support this verification.

Need reliable high-speed PCB layout support?

Connect Logic provides professional PCB layout and SI/PI simulation services for DDR4, DDR5, ATE, high-speed, RF, HDI, load boards, probe cards, and burn-in boards. Design smarter, route with confidence. See our capabilities or get in touch.