Advantest V93000 vs Teradyne UltraFLEX: A Load Board Design Guide

Why the platform shapes the layout

A load board, the Device Interface Board, or DIB, on both platforms, is not a generic PCB. It is a controlled-impedance instrument that must present the tester's pin electronics to the DUT with minimum distortion, deliver clean power under fast transient current, and survive thousands of insertions. (At wafer sort the equivalent hardware is the probe interface board, or PIB, and the probe card itself; the electrical problems overlap, but the mechanical ones do not.)

The mechanical interface, pogo arrangement, and channel allocation differ enough between the V93000 and UltraFLEX that the layout, stackup, and PDN strategy diverge from the very first floorplan.

Mechanical and interface constraints

Advantest V93000 (Smart Scale / EXA Scale)

• The DUT interface is circular, with a high-density pogo ring. Channel cards sit in the testhead card cage, 8, 16, 32, or 64 slots depending on the configuration, and connect up through the pogo tower, so critical high-speed nets are typically short but must fan in radially without crossing power domains.
• Card choice sets the loss budget. Wave Scale Millimeter pushes RF work into mmWave frequencies; on the digital side, Pin Scale Serial Link (PSSL) runs to 16 Gbps and Pin Scale 5000 delivers 5 Gbps scan. Any of these forces tight loss budgets and disciplined via engineering on every layer that carries the signal. Note that Pin Scale 1600, still the workhorse universal digital pin on many installed systems, tops out at 1.6 Gbps, a very different design problem, and one where over-engineering the stackup just adds cost.
• Board thickness is often 4.5, 5.0, or 6.0 mm. High-aspect-ratio vias become a real electrical and manufacturability concern, and backdrill depth tolerance, not the decision to backdrill, becomes the limiting variable.

Teradyne UltraFLEX

• Rectangular DIB with a fixed pogo/SureMate footprint. UltraFLEX uses a universal slot architecture, so any instrument can be installed in any slot: channels are grouped per instrument, but which physical slot a given instrument occupies is a program-level decision. That makes channelized routing and per-instrument power islands the right structure, while the actual path length to the DUT depends on the slot allocation you are handed.
• UltraSerial10G for high-speed serial, UltraPin1600/1600+ (to 2.2 Gbps) for high-density digital, and the HSD-M / HPM8G family define the loss and return-loss budget available at the DUT ball. That budget shrinks fast on a large DIB, so route length and via count matter as much as the dielectric.
• Stackups on UltraFLEX programs tend to be thinner than V93000 boards but with more signal layers, trading z-axis height for horizontal escape room.

A note on current generations

Both vendors have moved on, and new programs increasingly land on the newer platforms. Teradyne's UltraFLEXplus uses the Broadside DIB across all base systems for higher density, higher site counts, and simplified routing. Advantest's V93000 EXA Scale pairs Pin Scale 5000 digital with the XPS256 power supply card, and, importantly, maintains compatibility with existing V93000 load boards and Smart Scale cards. If you are planning a migration, that compatibility is design leverage: the DIB you build today can often follow the program forward, provided the stackup and PDN were specified against the next instrument generation rather than the current one.

Signal integrity: where the two platforms diverge

On the V93000 we design to the specified insertion-loss and return-loss budget of the actual channel card in the configuration, apportioning the load board's share against the cable and pogo contribution. In practice this means:

• Low-Dk / low-Df laminates (Megtron 6/7, Isola Tachyon 100G) on any layer carrying a high-speed net.
• Backdrilling high-speed via stubs, with remaining-stub length specified as a budget rather than a wish. On a 5–6 mm board, depth tolerance of roughly ±0.15 mm means you design for the worst-case residual stub, not the nominal one. Above ~20 GHz, that residual can dominate return loss on its own.
• Length matching to real, manufacturable tolerances. In a typical low-Dk stripline, propagation is on the order of 156 ps/inch, so 1 mil of length is roughly 0.16 ps, well inside etch and registration tolerance. We hold intra-pair skew on SerDes lanes to ±2–5 mil (~0.3–0.8 ps) and DDR/LPDDR intra-byte-group matching to ±10–25 mil (~1.5–4 ps), and we specify the constraint in picoseconds against the interface's skew budget wherever the customer's spec allows it.
• Reference-plane continuity across the pogo ring, with stitching vias adjacent to every signal via transition.

On UltraFLEX the failure mode is usually different. Signals often travel farther across the DIB before reaching the DUT, which makes crosstalk between channelized bundles and reflections at socket transitions the primary risks. Our default response:

• Dedicated return layers and via fencing between adjacent instrument bundles. (Guard traces alone are not a solution, an unstitched guard trace can couple more energy than it shields.)
• Impedance-controlled socket transitions modeled in 3D (HFSS / SIwave) rather than 2D field solvers.
• Per-instrument reference planes, so a noisy DC instrument cannot pollute an adjacent high-speed return path.

Power integrity and PDN

Modern devices under test pull tens to hundreds of amps with fast di/dt. The two platforms give you very different starting points.

V93000. DPS128 / DPS128HC channels are clean and low-noise, and AVI64 / FVI16 add per-pin and floating VI capability where the device needs it. But the radial interface geometry means the current path from the supply to the DUT is long. We compensate with wide, low-inductance copper on inner layers, aggressive via stitching under the socket, and staged decoupling, bulk, mid-frequency, and 0402 die-side caps in the pocket under the device.

UltraFLEX. The UVS256 (VHDVS), HexVS, VSM, UVI80, and DC30/DC75 instruments give you dense, accurate sourcing, but each carries a per-instrument current limit. High-current rails therefore get split across multiple instruments and rejoined on the DIB, and that merge is where PDN designs fail. Specifically:

• The plane cuts that isolate each instrument's sense path must not force return current through a high-inductance detour. Every cut needs a defined return strategy, not just a keepout.
• Remote sense connections have to be Kelvin-referenced at the socket, not at the merge point, or the instruments fight each other under transient load.
• Current sharing between merged instruments is only as good as the copper symmetry between them. Asymmetric spreading resistance shows up as one instrument hitting its limit while the others coast.

We verify with a PDN impedance simulation that the merged rail stays under target impedance across the full frequency range of the load transient, not just at DC and not just at the socket, but at the merge node itself.

Thermal and mechanical

• V93000 DIBs bolt into a heavy stiffener; expect flatness callouts on the order of 0.05 mm across the socket region for fine-pitch BGA / WLCSP work. (Flatness is a form tolerance with a single total zone, specify it as such, not as a bilateral ± value, or fab will interpret it however is cheapest.)
• UltraFLEX DIBs see more thermal cycling near instrument connectors. We add copper balancing per layer to control warpage.
• On both platforms, current-density hot spots around the DUT socket need CFD, or at minimum an analytical thermal review, before fabrication.

Validation flow we run on both

1. Pre-layout SI/PI constraint definition derived from the actual channel and power budget of the configured instruments.
2. Stackup and via structure optimization in SIwave / HFSS.
3. Post-route S-parameter extraction and channel simulation, using IBIS models for the digital instruments and IBIS-AMI where the DUT vendor supplies equalized SerDes models.
4. PDN impedance simulation across the full frequency range of the load transient, including any multi-instrument rail merge.
5. Thermal review under worst-case DC instrument current.

Bottom line

The V93000 rewards short, radial routing with world-class laminates and disciplined via engineering. UltraFLEX rewards clean channelization, per-instrument isolation, and a rail-merge strategy that survives simulation. Both punish shortcuts. A load board designed generically for "high-speed ATE" will underperform on one or both platforms; a load board designed to the specific loss and PDN model of the configured instruments will hold yield at first silicon.