Organic (MLO) & ceramic (MLC) substrate and interposer design for wafer testing—coreless options, low‑parasitic fan‑outs, RF up to 80 GHz, high current to 600 A, and DFM aligned to foundry specs.
MLC Substrate Design Services
We design production‑ready MLO/MLC substrates and interposers for wafer testing and package evaluation. Coreless stackups, low‑parasitic routing, and clean return paths keep the substrate transparent—so your silicon sets the performance.
What we design
- Organic (MLO) & Ceramic (MLC) substrates
- Coreless substrates
- Interposers for wafer testing
Die styles
- Flip‑chip
- Wirebond
- Single‑ and multi‑die
Capabilities & performance
- Dense fan‑outs with controlled impedance and tight return‑path control
- RF to 80 GHz with SI/PI & RF co‑simulation
- High current to 600 A (wide copper, via stitching, thermal relief)
- DFM/DFT aligned to leading foundry specifications; manufacturable stackups
So timing and loss are set by your silicon, not by the interposer.
50% OFF your first load board / high‑speed digital PCB
PCB layout and simulation that interfaces your DUT to the tester (e.g., Teradyne J750, Ultraflex/Ultraflex Plus, Advantest 93K, T2000, NI STS), optimized for signal integrity and power delivery
Yes—pre‑layout SI/PI rules plus IBIS‑AMI, TDR, S‑parameters, eye diagrams for DDR/PCIe/USB/MIPI and SERDES to 112 Gbps
Typical 1–3 weeks depending on complexity; rush options available.
Yes—controlled impedance ±5%, RF/microwave routing, HDI microvias, and back‑drill for stub removal; co‑simulation (S‑parameters/TDR) as needed.
Stackup & constraints, Gerbers/ODB++, drill, fab/assembly notes, BOM (as needed), and simulation reports.
Yes—we tune materials, stackups, and routing rules for Teradyne/Advantest/NI resources.
We serve globally, primarily the USA, plus Canada, Europe, Singapore, Malaysia, Taiwan, Germany, and Japan.
Absolutely—we work under your NDA and keep data protected.