HDI microvias + RF/microwave layout to 40 GHz and SERDES to 112 Gbps—controlled impedance, EMI/EMC, hybrid stackups.
HDI & RF PCB Expertise
At high speeds, little things become big problems—reflections, insertion loss, mode conversion, and EMI can tank margins and spin debug loops. We design HDI + RF boards that behave: controlled‑impedance stackups, stitched return paths, microvias/back‑drill to kill stubs, and clean routing that keeps eyes open and emissions in check.
Key Features (built on real HDI PCB & RF expertise)
- Interfaces: DDR2/3/4, USB, PCIe, SATA, HDMI, LVDS, MIPI, SERDES up to 112 Gbps
- HDI: microvia stacks (1–3), stacked or staggered, blind/buried/stack vias; 0.4 / 0.315 mm pitch BGAs; 0.1 mm microvia drills
- Hybrid stackups: stripline & microstrip mixes, even/odd layer stacks; thickness 0.92–6.35 mm
- Impedance control: ±5% targets (50/90/100 Ω), multi‑impedance on the same layer; tuned neck‑downs & pair routing
- Loss & skew control: length reduction, matched‑length groups, phase/length tuning; arc routing where RF prefers it
- Return‑path integrity: ground separation, via stitching, copper‑to‑trace spacing by frequency; back‑drill or blind/buried to remove stubs
- PDN/decoupling: optimized capacitor profile by frequency, low‑Z rails (Z11), loop‑inductance reduction
- EMI/EMC: shielding strategies, clean reference planes, crosstalk control (NEXT/FEXT) verified by simulation
- Layer counts: 6–48 typical for HDI; broader stacks available per device and fab rules
So link performance is defined by your device, not by vias and return‑path gaps.
Special Offer — 50% OFF Your First Design
PCB layout and simulation that interfaces your DUT to the tester (e.g., Teradyne J750, Ultraflex/Ultraflex Plus, Advantest 93K, T2000, NI STS), optimized for signal integrity and power delivery
Yes—pre‑layout SI/PI rules plus IBIS‑AMI, TDR, S‑parameters, eye diagrams for DDR/PCIe/USB/MIPI and SERDES to 112 Gbps
Typical 1–3 weeks depending on complexity; rush options available.
Yes—controlled impedance ±5%, RF/microwave routing, HDI microvias, and back‑drill for stub removal; co‑simulation (S‑parameters/TDR) as needed.
Stackup & constraints, Gerbers/ODB++, drill, fab/assembly notes, BOM (as needed), and simulation reports.
Yes—we tune materials, stackups, and routing rules for Teradyne/Advantest/NI resources.
We serve globally, primarily the USA, plus Canada, Europe, Singapore, Malaysia, Taiwan, Germany, and Japan.
Absolutely—we work under your NDA and keep data protected.